Rcomp-kaniw: Difference between revisions
doytdeuter (talk | contribs) Created page with "Rcomp-kaniw is a 4-bit computer project in the town of Kaniw, Ukraine. The machine has been allocated a 2x3 chunk area. == Functions == '''ALU FUNCTIONS''' ''0'': Load DataBus 1 into Adder 1 as input A ''1'': Load DataBus 2 into Adder 1 as input B ''2'': Load DataBus 1 into Adder 2 as input A ''3'': Load DataBus 2 into Adder 2 as input B ''4'': Load DataBus 1 into Multiplier as input A ''5'': Load DataBus 2 into Multiplier as input B ''6'': Load DataBus 1 in..." |
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''D'': Write CalcBus 1 on Register 2 | ''D'': Write CalcBus 1 on Register 2 | ||
Rcomp-kaniw is a 4-bit computer project in the town of [[Kaniw]], Ukraine. The machine has been allocated a 2x3 chunk area. | |||
== Functions == | |||
=== ALU FUNCTIONS === | |||
'''0''': Load DataBus 1 into Adder 1 as input A | |||
'''1''': Load DataBus 2 into Adder 1 as input B | |||
'''2''': Load DataBus 1 into Adder 2 as input A | |||
'''3''': Load DataBus 2 into Adder 2 as input B | |||
'''4''': Load DataBus 1 into Multiplier as input A | |||
'''5''': Load DataBus 2 into Multiplier as input B | |||
'''6''': Load DataBus 1 into Bitwise_Calculator as input A | |||
'''7''': Load Databus 2 into Bitwise_Calculator as input B | |||
'''8''': Run operation: Adder 1 (loads output into CalcBus 1) | |||
'''9''': Run operation: Adder 2 (loads output into CalcBus 1) | |||
'''A''': Run operation: Adder 1 as negative operation (loads output into CalcBus 1) | |||
'''B''': Run operation: Adder 2 as negative operation (loads output into CalcBus 1) | |||
'''C''': Run operation Multiplier (loads output into CalcBus 1) | |||
'''D''': Run operation Bitwise_Calculator as & (and) operation (loads output into CalcBus 1) | |||
'''E''': Run operation Bitwise_Calculator as ^ (xor) operation (loads output into CalcBus 1) | |||
'''F''': Run operation Bitwise_Calculator as | (or) operation (loads output into CalcBus 1) | |||
=== RAM FUNCTIONS === | |||
'''0''': Write USERINPUT on Register 1 | |||
'''1''': Write USERINPUT on Register 2 | |||
'''2''': Write USERINPUT on Register 3 | |||
'''3''': Write USERINPUT on Register 4 | |||
'''4''': Read Register 1 into DataBus 1 | |||
'''5''': Read Register 1 into DataBus 2 | |||
'''6''': Read Register 2 into DataBus 1 | |||
'''7''': Read Register 2 into DataBus 2 | |||
'''8''': Read Register 3 into DataBus 1 | |||
'''9''': Read Register 3 into DataBus 2 | |||
'''A''': Read Register 4 into DataBus 1 | |||
'''B''': Read Register 4 into DataBus 2 | |||
'''C''': Write CalcBus 1 on Register 1 | |||
'''D''': Write CalcBus 1 on Register 2 | |||
'''E''': Write CalcBus 1 on Register 3 | |||
'''F''': Write CalcBus 1 on Register 4 | |||
=== PROGRAM RUNNER FUNCTIONS === | |||
==== REGULAR ==== | |||
'''0X''': Runs the ALU function, where X is the hexidecimal of the ALU function index. | |||
'''1X''': Runs the RAM function, where X is the hexidecimal of the RAM function index. | |||
'''2-''': Does nothing in this clock cycle, practically acts as a wait/sleep. | |||
'''3XX''': Jumps to the instruction at address XX | |||
'''5XX''': Jumps to the instruction if the condition bus is True. | |||
'''6XX''': Jumps to the instruction if the condition bus is False. | |||
'''7X''': Sets condition bus to True if Register A (index: last 2 bits of X) > Register B (index: first 2 bits of X) | |||
'''8X''': Sets condition bus to True if Register A (index: last 2 bits of X) < Register B (index: first 2 bits of X) | |||
'''9X''': Sets condition bus to True if Register A (index: last 2 bits of X) == Register B (index: first 2 bits of X) | |||
'''A-''': Halts the program | |||
'''B-''': Starts the program (this is fired externally, from USERINPUT) | |||
==== CANVAS ==== | |||
'''C-''': Toggles pixel @ index (index: read from Register 1) | |||
'''D-''': Toggles pixel @ index (index: read from Register 2) | |||
'''E-''': Toggles pixel @ index (index: read from Register 3) | |||
'''F-''': Toggles pixel @ index (index: read from Register 4) | |||
== Helpers == | |||
[[File:Doytschreal2.png]] [[DoytschReal]]: resources, design, area | |||
== Sponsors == | |||
[[File:Doytschreal2.png]] [[DoytschReal]] | |||
''E'': Write CalcBus 1 on Register 3 | ''E'': Write CalcBus 1 on Register 3 | ||