Rcomp-kaniw
About
Rcomp-kaniw is a 4-bit redstone computer project in the town of [Aurora:Kaniw|Kaniw], in central Ukraine.
Note: When ticks are mentioned in this thread, it reffers to redstone ticks per second, which is the total tps / 2. Average servers have a 10 redstone tick per seconds, but EMC has about 5-7.
Specs
Clock: 3 tick on, 3 tick off [around 2-3 Hz] Memory read/write delay: 2 ticks
Hardware (planned)
Primary Bus (PBUS)': A bus connected to most components [4bit bus]
Secondary Bus (SBUS): Secondary bus connected to most components [4bit bus]
Instruction Bus (IBUS): Used to transfer instruction data to ALL components. Each component is fitted with a specialised gate that when the right signal is given, turns on the component
Excess Bus (EBUS): A bus for holding an additional 4 bits alongside PBUS or SBUS, used when the output is over 4 bits [4bit bus]
Comparator Bus (CBUS): Holds the results from the last operation by CMP [3bit bus]
Arithmetic Unit (AU): Performs 4-bit addition and subtraction.
Bitwise Unit (BU): Performs 4-bit bitwise operations of OR, AND, XOR, NOT
Comparator (CMP): Performs comparason operations on two inputs and outputs them on CBUS (>, <, ==)
Multiplier (CMP): Performs multiplication operation on two inputs. Output may be over 4 bits, bits 3-7 are loaded onto EBUS
Memory (MEM): Can output to either PBUS or SBUS, contains 16 registers that each store 4 bits (a nibble)
Clock (C): Turns on and off continuesly to keep all components in sync
User input (USIN): 4-bit interface allowing direct user input into the computer
Instruction ROM (IROM): Read only memory, holds upto 32 lines of instructions
Instruction list (4 bit)
Instruction Name: address, arguements , Description
NON: 0, no arguements, "Does nothing"
READ: 1, (arg1: memAddress [4bit], arg2: bus [1bit]), "Reads from memAddress and loads the data into PBUS if arg2 is 0, else loads into SBUS"
WRITE: 2, (arg1: memAddress [4bit], arg2: bus [2bit]), "Writes to memAddress from bus, 00: PBUS, 01: SBUS, 10: EBUS, 11: IBUS"
ADD: 3, (arg1: fromMemAddress [4bit], arg2: fromMemAddress [4bit]), "Performs ADD operation on values stored in MEM, with arg1 and arg2 being their addresses"
SUB: 4, (arg1: fromMemAddress [4bit], arg2: fromMemAddress [4bit]), "Performs SUB operation on values stored in MEM, with ang1 and arg2 being their addresses"
MUL: 5, (arg1: fromMemAddress [4bit], arg2: fromMemAddress[4bit]), "Performs MUL operation on values stored in MEM, with arg1 and arg2 being their addresses. THE OUTPUT OF THIS IS SPLIT INTO TWO BUSES, PBUS or bits 0-3 and EBUS for bits 4-7"
BOR: 6, (arg1: fromMemAddress [4bit], arg2: fromMemAddress[4bit]), "Performs bitwise OR operation on values stored in MEM, with ang1 and arg2 being their addresses"
BAND: 7, (arg1: fromMemAddress [4bit], arg2: fromMemAddress[4bit]), "Performs bitwise AND operation on values stored in MEM, with ang1 and arg2 being their addresses"
BXOR: 8, (arg1: fromMemAddress [4bit], arg2: fromMemAddress[4bit]), "Performs bitwise XOR operation on values stored in MEM, with ang1 and arg2 being their addresses"
BNOT: 9, (arg1: fromMemAddress [4bit]), "Performs bitwise NOT operation on values stored in MEM, with ang1 being the address"
JMP: A, (arg1: line [5bit]), "Unconditionally jumps to the line given"
JMPIF: B, (arg1: line [5bit], arg2: compare [2bit]), "Jumps to line IF CBUS @ arg2 is TRUE"
JMPIFNOT: C, (arg1: line [5bit], arg2: compare[2bit]), "Jumps to line IF CBUS @ arg2 is FALSE"
SWAPBUS: D: no arguements, "Swaps the data in PBUS and SBUS"
HALT: E: no arguements, "Unconditionally halts the program"
Stakeholders
Contributes: design, resources, land (owns Kaniw)
Contributes: design