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| Rcomp-kaniw is a 4-bit computer project in the town of [[File:kaniw_flag.png|10px]] [[Aurora:Kaniw|Kaniw]], Ukraine. The machine has been allocated a 2x3 chunk area on the border with the neighbouring town of Cherkassy.
| | == About == |
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| == Components ==
| | Rcomp-kaniw is a 4-bit redstone computer project in the town of [[Aurora:Kaniw|Kaniw]], in central Ukraine. |
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| === Buses ===
| | Note: When ticks are mentioned in this thread, it reffers to redstone ticks per second, which is the total tps / 2. Average servers have a 10 redstone tick per seconds, but EMC has about 5-7. |
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| ==== DataBus 1 ==== | | == Specs == |
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| Purpose: Loads Data into Arithmetic/Bitwise components.
| | Clock: 3 tick on, 3 tick off [around 2-3 Hz] |
| | Memory read/write delay: 2 ticks |
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| Size: 4-bit
| | == Hardware (planned) == |
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| Writes to: Adder 1, Adder 2, Multiplier, 3-function Bitwise
| | '''Primary Bus (PBUS)'''': A bus connected to most components [4bit bus] |
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| Reads from: Register 1, Register 2, Register 3, Register 4
| | '''Secondary Bus (SBUS)''': Secondary bus connected to most components [4bit bus] |
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| ==== DataBus 2 ====
| | '''Instruction Bus (IBUS)''': Used to transfer instruction data to ALL components. Each component is fitted with a specialised gate that when the right signal is given, turns on the component |
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| Purpose: Loads Data into Arithmetic/Bitwise components.
| | '''Excess Bus (EBUS)''': A bus for holding an additional 4 bits alongside PBUS or SBUS, used when the output is over 4 bits [4bit bus] |
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| Size: 4-bit
| | '''Comparator Bus (CBUS)''': Holds the results from the last operation by CMP [3bit bus] |
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| Writes to: Adder 1, Adder 2, Multiplier, 3-function Bitwise
| | '''Arithmetic Unit (AU)''': Performs 4-bit addition and subtraction. |
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| Reads from: Register 1, Register 2, Register 3, Register 4
| | '''Bitwise Unit (BU)''': Performs 4-bit bitwise operations of OR, AND, XOR, NOT |
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| ==== CalcBus 1 ==== | | '''Comparator (CMP)''': Performs comparason operations on two inputs and outputs them on CBUS (>, <, ==) |
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| Purpose: Loads Data from Arithmetic/Bitwise components to Registers
| | '''Multiplier (CMP)''': Performs multiplication operation on two inputs. Output may be over 4 bits, bits 3-7 are loaded onto EBUS |
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| Writes to: Register 1, Register 2, Register 3, Register 4
| | '''Memory (MEM)''': Can output to either PBUS or SBUS, contains 16 registers that each store 4 bits (a nibble) |
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| Reads from: Adder 1, Adder 2, Multiplier, 3-function Bitwise
| | '''Clock (C)''': Turns on and off continuesly to keep all components in sync |
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| ==== condition bus
| | '''User input (USIN)''': 4-bit interface allowing direct user input into the computer |
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| Purpose: Holds a 1 bit value if the previous condition operation was true (==, <, >)
| | '''Instruction ROM (IROM)''': Read only memory, holds upto 32 lines of instructions |
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| Leads to: Program counter (not written)
| | == Instruction list (4 bit) == |
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| Reads from: Comparator
| | Instruction Name: address, arguements , Description |
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| === Arithmetic ===
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| '''Adder 1''': (CCA design, 4-bit) | | '''NON''': 0, no arguements, "Does nothing" |
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| '''Adder 2''': (CCA design, 4-bit) | | '''READ''': 1, (arg1: memAddress [4bit], arg2: bus [1bit]), "Reads from memAddress and loads the data into PBUS if arg2 is 0, else loads into SBUS" |
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| '''Multiplier''': (standard design, 4-bit) | | '''WRITE''': 2, (arg1: memAddress [4bit], arg2: bus [2bit]), "Writes to memAddress from bus, 00: PBUS, 01: SBUS, 10: EBUS, 11: IBUS" |
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| '''3-function Bitwise''': (MUX + AND + OR + XOR gates, 4-bit) | | '''ADD''': 3, (arg1: fromMemAddress [4bit], arg2: fromMemAddress [4bit]), "Performs ADD operation on values stored in MEM, with arg1 and arg2 being their addresses" |
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| === Storage ===
| | '''SUB''': 4, (arg1: fromMemAddress [4bit], arg2: fromMemAddress [4bit]), "Performs SUB operation on values stored in MEM, with ang1 and arg2 being their addresses" |
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| '''Register A''': (Index: 00, Capacity: 4-bit) | | '''MUL''': 5, (arg1: fromMemAddress [4bit], arg2: fromMemAddress[4bit]), "Performs MUL operation on values stored in MEM, with arg1 and arg2 being their addresses. THE OUTPUT OF THIS IS SPLIT INTO TWO BUSES, PBUS or bits 0-3 and EBUS for bits 4-7" |
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| '''Register B''': (Index: 01, Capacity: 4-bit) | | '''BOR''': 6, (arg1: fromMemAddress [4bit], arg2: fromMemAddress[4bit]), "Performs bitwise OR operation on values stored in MEM, with ang1 and arg2 being their addresses" |
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| '''Register C''': (Index: 10, Capacity: 4-bit) | | '''BAND''': 7, (arg1: fromMemAddress [4bit], arg2: fromMemAddress[4bit]), "Performs bitwise AND operation on values stored in MEM, with ang1 and arg2 being their addresses" |
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| '''Register D''': (Index : 11, Capacity: 4-bit) | | '''BXOR''': 8, (arg1: fromMemAddress [4bit], arg2: fromMemAddress[4bit]), "Performs bitwise XOR operation on values stored in MEM, with ang1 and arg2 being their addresses" |
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| === Comparator ===
| | '''BNOT''': 9, (arg1: fromMemAddress [4bit]), "Performs bitwise NOT operation on values stored in MEM, with ang1 being the address" |
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| '''Equal to (==)''': (4-bit) | | '''JMP''': A, (arg1: line [5bit]), "Unconditionally jumps to the line given" |
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| '''Greater Than (>)''': (4-bit) | | '''JMPIF''': B, (arg1: line [5bit], arg2: compare [2bit]), "Jumps to line IF CBUS @ arg2 is TRUE" |
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| '''Less Than (<)''': (4-bit) | | '''JMPIFNOT''': C, (arg1: line [5bit], arg2: compare[2bit]), "Jumps to line IF CBUS @ arg2 is FALSE" |
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| == Functions ==
| | '''SWAPBUS''': D: no arguements, "Swaps the data in PBUS and SBUS" |
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| === ALU FUNCTIONS ===
| | '''HALT''': E: no arguements, "Unconditionally halts the program" |
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| '''0''': Load DataBus 1 into Adder 1 as input A
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| '''1''': Load DataBus 2 into Adder 1 as input B
| | == Stakeholders == |
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| '''2''': Load DataBus 1 into Adder 2 as input A
| | [[File:Doytschreal2.png]] [[DoytschReal|doytschReal]] |
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| '''3''': Load DataBus 2 into Adder 2 as input B
| | Contributes: design, resources, land (owns Kaniw) |
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| '''4''': Load DataBus 1 into Multiplier as input A
| | [[Kv4x|kv4x]] |
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| '''5''': Load DataBus 2 into Multiplier as input B
| | Contributes: design |
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| '''6''': Load DataBus 1 into Bitwise_Calculator as input A
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| '''7''': Load Databus 2 into Bitwise_Calculator as input B
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| '''8''': Run operation: Adder 1 (loads output into CalcBus 1)
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| '''9''': Run operation: Adder 2 (loads output into CalcBus 1)
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| '''A''': Run operation: Adder 1 as negative operation (loads output into CalcBus 1)
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| '''B''': Run operation: Adder 2 as negative operation (loads output into CalcBus 1)
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| '''C''': Run operation Multiplier (loads output into CalcBus 1)
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| '''D''': Run operation Bitwise_Calculator as & (and) operation (loads output into CalcBus 1)
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| '''E''': Run operation Bitwise_Calculator as ^ (xor) operation (loads output into CalcBus 1)
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| '''F''': Run operation Bitwise_Calculator as | (or) operation (loads output into CalcBus 1)
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| === RAM FUNCTIONS ===
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| '''0''': Write USERINPUT on Register 1
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| '''1''': Write USERINPUT on Register 2
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| '''2''': Write USERINPUT on Register 3
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| '''3''': Write USERINPUT on Register 4
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| '''4''': Read Register 1 into DataBus 1
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| '''5''': Read Register 1 into DataBus 2
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| '''6''': Read Register 2 into DataBus 1
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| '''7''': Read Register 2 into DataBus 2
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| '''8''': Read Register 3 into DataBus 1
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| '''9''': Read Register 3 into DataBus 2
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| '''A''': Read Register 4 into DataBus 1
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| '''B''': Read Register 4 into DataBus 2
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| '''C''': Write CalcBus 1 on Register 1
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| '''D''': Write CalcBus 1 on Register 2
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| '''E''': Write CalcBus 1 on Register 3
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| '''F''': Write CalcBus 1 on Register 4
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| === PROGRAM RUNNER FUNCTIONS ===
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| ==== REGULAR ====
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| '''0X''': Runs the ALU function, where X is the hexidecimal of the ALU function index.
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| '''1X''': Runs the RAM function, where X is the hexidecimal of the RAM function index.
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| '''2-''': Does nothing in this clock cycle, practically acts as a wait/sleep.
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| '''3XX''': Jumps to the instruction at address XX
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| '''5XX''': Jumps to the instruction if the condition bus is True.
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| '''6XX''': Jumps to the instruction if the condition bus is False.
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| ==== COMPARASON ====
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| '''7X''': Sets condition bus to True if Register A (index: last 2 bits of X) > Register B (index: first 2 bits of X)
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| '''8X''': Sets condition bus to True if Register A (index: last 2 bits of X) < Register B (index: first 2 bits of X)
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| '''9X''': Sets condition bus to True if Register A (index: last 2 bits of X) == Register B (index: first 2 bits of X)
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| ==== PROGRAM STATUS ====
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| '''A-''': Halts the program
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| '''B-''': Starts the program (this is fired externally, from USERINPUT)
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| ==== CANVAS ====
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| '''C-''': Toggles pixel @ index (index: read from Register 1)
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| '''D-''': Toggles pixel @ index (index: read from Register 2)
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| '''E-''': Toggles pixel @ index (index: read from Register 3)
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| '''F-''': Toggles pixel @ index (index: read from Register 4)
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| == Other Info ==
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| When Adder 1 or Adder 2 perform the negation operation, The range of values that a single hexidecimal value can represent shifts from 0 to 15 to -8 to 7, making bit 3 worth -8 and not 8. If bit 3 is still represented as 8, then the negation operation would simply not be true.
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| Carry-Outs from Adder1 & Adder2 are ignored, as a 5-bit output can't be loaded on a 4-bit bus.
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| Multipliers can be toggled to either output their first 4 bits, or last 4 bits.
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| == Helpers ==
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| [[File:Doytschreal2.png]] [[DoytschReal]]: Computer design, Computer construction, Area preperation/Escavation.
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| == Sponsors ==
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| [[File:Doytschreal2.png]] [[DoytschReal]]: Resources & Components.
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