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Rcomp-kaniw (Short for Redstone Computer of Kaniw) is a 4-bit computer project in the town of [[File:kaniw_flag.png|10px]] [[Aurora:Kaniw|Kaniw]], Ukraine. The machine has been allocated a 2x3 chunk area on the border with the neighbouring town of Cherkassy.
== About ==


Rcomp-kaniw is a 4-bit redstone computer project in the town of [[Aurora:Kaniw|Kaniw]], in central Ukraine.


== Target Specs ==
Note: When ticks are mentioned in this thread, it reffers to redstone ticks per second, which is the total tps / 2. Average servers have a 10 redstone tick per seconds, but EMC has about 5-7.


'''rtps per function execute''': 5-10 (1-2s, with server usually being at 5 rtps)
== Specs ==


== Components ==
Clock: 3 tick on, 3 tick off [around 2-3 Hz]
Memory read/write delay: 2 ticks


=== Buses ===
== Hardware (planned) ==


==== DataBus 1 ====
'''Primary Bus (PBUS)'''': A bus connected to most components [4bit bus]


Purpose: Loads Data into Arithmetic/Bitwise components.
'''Secondary Bus (SBUS)''': Secondary bus connected to most components [4bit bus]


Size: 4-bit
'''Instruction Bus (IBUS)''': Used to transfer instruction data to ALL components. Each component is fitted with a specialised gate that when the right signal is given, turns on the component


Writes to: Adder 1, Adder 2, Multiplier, 3-function Bitwise
'''Excess Bus (EBUS)''': A bus for holding an additional 4 bits alongside PBUS or SBUS, used when the output is over 4 bits [4bit bus]


Reads from: Register 1, Register 2, Register 3, Register 4
'''Comparator Bus (CBUS)''': Holds the results from the last operation by CMP [3bit bus]


==== DataBus 2 ====
'''Arithmetic Unit (AU)''': Performs 4-bit addition and subtraction.


Purpose: Loads Data into Arithmetic/Bitwise components.
'''Bitwise Unit (BU)''': Performs 4-bit bitwise operations of OR, AND, XOR, NOT


Size: 4-bit
'''Comparator (CMP)''': Performs comparason operations on two inputs and outputs them on CBUS (>, <, ==)


Writes to: Adder 1, Adder 2, Multiplier, 3-function Bitwise
'''Multiplier (CMP)''': Performs multiplication operation on two inputs. Output may be over 4 bits, bits 3-7 are loaded onto EBUS


Reads from: Register 1, Register 2, Register 3, Register 4
'''Memory (MEM)''': Can output to either PBUS or SBUS, contains 16 registers that each store 4 bits (a nibble)


==== CalcBus 1 ====
'''Clock (C)''': Turns on and off continuesly to keep all components in sync


Purpose: Loads Data from Arithmetic/Bitwise components to Registers
'''User input (USIN)''': 4-bit interface allowing direct user input into the computer


Writes to: Register 1, Register 2, Register 3, Register 4
'''Instruction ROM (IROM)''': Read only memory, holds upto 32 lines of instructions


Reads from: Adder 1, Adder 2, Multiplier, 3-function Bitwise
== Instruction list (4 bit) ==


==== condition bus
Instruction Name: address, arguements , Description


Purpose: Holds a 1 bit value if the previous condition operation was true (==, <, >)


Leads to: Program counter (not written)
'''NON''': 0, no arguements, "Does nothing"


Reads from: Comparator
'''READ''': 1, (arg1: memAddress [4bit], arg2: bus [1bit]), "Reads from memAddress and loads the data into PBUS if arg2 is 0, else loads into SBUS"


=== Arithmetic ===
'''WRITE''': 2, (arg1: memAddress [4bit], arg2: bus [2bit]), "Writes to memAddress from bus, 00: PBUS, 01: SBUS, 10: EBUS, 11: IBUS"


'''Adder 1''': (CCA design, 4-bit)
'''ADD''': 3, (arg1: fromMemAddress [4bit], arg2: fromMemAddress [4bit]), "Performs ADD operation on values stored in MEM, with arg1 and arg2 being their addresses"


'''Adder 2''': (CCA design, 4-bit)
'''SUB''': 4, (arg1: fromMemAddress [4bit], arg2: fromMemAddress [4bit]), "Performs SUB operation on values stored in MEM, with ang1 and arg2 being their addresses"


'''Multiplier''': (standard design, 4-bit)
'''MUL''': 5, (arg1: fromMemAddress [4bit], arg2: fromMemAddress[4bit]), "Performs MUL operation on values stored in MEM, with arg1 and arg2 being their addresses. THE OUTPUT OF THIS IS SPLIT INTO TWO BUSES, PBUS or bits 0-3 and EBUS for bits 4-7"


'''3-function Bitwise''': (MUX + AND + OR + XOR gates, 4-bit)
'''BOR''': 6, (arg1: fromMemAddress [4bit], arg2: fromMemAddress[4bit]), "Performs bitwise OR operation on values stored in MEM, with ang1 and arg2 being their addresses"


=== Storage ===
'''BAND''': 7, (arg1: fromMemAddress [4bit], arg2: fromMemAddress[4bit]), "Performs bitwise AND operation on values stored in MEM, with ang1 and arg2 being their addresses"


'''Register A''': (Index: 00, Capacity: 4-bit)
'''BXOR''': 8, (arg1: fromMemAddress [4bit], arg2: fromMemAddress[4bit]), "Performs bitwise XOR operation on values stored in MEM, with ang1 and arg2 being their addresses"


'''Register B''': (Index: 01, Capacity: 4-bit)
'''BNOT''': 9, (arg1: fromMemAddress [4bit]), "Performs bitwise NOT operation on values stored in MEM, with ang1 being the address"


'''Register C''': (Index: 10, Capacity: 4-bit)
'''JMP''': A, (arg1: line [5bit]), "Unconditionally jumps to the line given"


'''Register D''': (Index : 11, Capacity: 4-bit)
'''JMPIF''': B, (arg1: line [5bit], arg2: compare [2bit]), "Jumps to line IF CBUS @ arg2 is TRUE"


=== Comparator ===
'''JMPIFNOT''': C, (arg1: line [5bit], arg2: compare[2bit]), "Jumps to line IF CBUS @ arg2 is FALSE"


'''Equal to (==)''': (4-bit)
'''SWAPBUS''': D: no arguements, "Swaps the data in PBUS and SBUS"


'''Greater Than (>)''': (4-bit)
'''HALT''': E: no arguements, "Unconditionally halts the program"


'''Less Than (<)''': (4-bit)


== Functions ==
== Stakeholders ==


=== ALU FUNCTIONS ===
[[File:Doytschreal2.png]] [[DoytschReal|doytschReal]]


'''0''': Load DataBus 1 into Adder 1 as input A
Contributes: design, resources, land (owns Kaniw)


'''1''': Load DataBus 2 into Adder 1 as input B
[[Kv4x|kv4x]]


'''2''': Load DataBus 1 into Adder 2 as input A
Contributes: design
 
'''3''': Load DataBus 2 into Adder 2 as input B
 
'''4''': Load DataBus 1 into Multiplier as input A
 
'''5''': Load DataBus 2 into Multiplier as input B
 
'''6''': Load DataBus 1 into Bitwise_Calculator as input A
 
'''7''': Load Databus 2 into Bitwise_Calculator as input B
 
'''8''': Run operation: Adder 1 (loads output into CalcBus 1)
 
'''9''': Run operation: Adder 2 (loads output into CalcBus 1)
 
'''A''': Run operation: Adder 1 as negative operation (loads output into CalcBus 1)
 
'''B''': Run operation: Adder 2 as negative operation (loads output into CalcBus 1)
 
'''C''': Run operation Multiplier (loads output into CalcBus 1)
 
'''D''': Run operation Bitwise_Calculator as & (and) operation (loads output into CalcBus 1)
 
'''E''': Run operation Bitwise_Calculator as ^ (xor) operation (loads output into CalcBus 1)
 
'''F''': Run operation Bitwise_Calculator as | (or) operation (loads output into CalcBus 1)
 
=== RAM FUNCTIONS ===
 
'''0''': Write USERINPUT on Register 1
 
'''1''': Write USERINPUT on Register 2
 
'''2''': Write USERINPUT on Register 3
 
'''3''': Write USERINPUT on Register 4
 
'''4''': Read Register 1 into DataBus 1
 
'''5''': Read Register 1 into DataBus 2
 
'''6''': Read Register 2 into DataBus 1
 
'''7''': Read Register 2 into DataBus 2
 
'''8''': Read Register 3 into DataBus 1
 
'''9''': Read Register 3 into DataBus 2
 
'''A''': Read Register 4 into DataBus 1
 
'''B''': Read Register 4 into DataBus 2
 
'''C''': Write CalcBus 1 on Register 1
 
'''D''': Write CalcBus 1 on Register 2
 
'''E''': Write CalcBus 1 on Register 3
 
'''F''': Write CalcBus 1 on Register 4
 
=== PROGRAM RUNNER FUNCTIONS ===
 
==== REGULAR ====
 
'''0XX''': Runs the ALU function, where X is the hexidecimal of the ALU function index.
 
'''1XX''': Runs the RAM function, where X is the hexidecimal of the RAM function index.
 
'''2--''': Does nothing in this clock cycle, practically acts as a wait/sleep.
 
'''3XX''': Jumps to the instruction at address XX
 
'''5XX''': Jumps to the instruction if the condition bus is True.
 
'''6XX''': Jumps to the instruction if the condition bus is False.
 
==== COMPARASON ====
 
'''7X1''': Sets condition bus to True if Register A (index: last 2 bits of X) > Register B (index: first 2 bits of X)
 
'''7X2''': Sets condition bus to True if Register A (index: last 2 bits of X) < Register B (index: first 2 bits of X)
 
'''7X3''': Sets condition bus to True if Register A (index: last 2 bits of X) == Register B (index: first 2 bits of X)
 
==== PROGRAM STATE ====
 
'''80-''': Halts the program indefinetely
 
'''81-''': Starts the program (this is fired externally, from USERINPUT)
 
'''81X''': Halts if A > B (A is the first 2 bits of X), (B is the last 2 bits of X)
 
'''82X''': Halts if A < B (A is the first 2 bits of X), (B is the last 2 bits of X)
 
'''83X''': Halfs if A == B (A is the first 2 bits of X), (B is the last 2 bits of X)
 
==== CANVAS ====
 
'''9X- (x: 0-3)''': Selects an index of a pixel to modify, X being the address where the index is stored (between 0-3)
 
'''94-''': Turns the lamp @ index on.
 
'''95-''': Turns the lamp @ index off.
 
'''96-''': Fetches the state of the lamp, which goes to condition bus.
 
== Other Info ==
 
When Adder 1 or Adder 2 perform the negation operation, The range of values that a single hexidecimal value can represent shifts from 0 to 15 to -8 to 7, making bit 3 worth -8 and not 8. If bit 3 is still represented as 8, then the negation operation would simply not be true.
 
Carry-Outs from Adder1 & Adder2 are ignored, as a 5-bit output can't be loaded on a 4-bit bus.
 
Multipliers can be toggled to either output their first 4 bits, or last 4 bits.
 
== Helpers ==
 
[[File:Doytschreal2.png]] [[DoytschReal|doytschReal]]: Computer design, Computer construction, Area preperation/Escavation.
 
 
== Sponsors ==
 
[[File:Doytschreal2.png]] [[DoytschReal|doytschReal]]: Resources & Components.

Latest revision as of 19:08, 11 December 2023

About

Rcomp-kaniw is a 4-bit redstone computer project in the town of Kaniw, in central Ukraine.

Note: When ticks are mentioned in this thread, it reffers to redstone ticks per second, which is the total tps / 2. Average servers have a 10 redstone tick per seconds, but EMC has about 5-7.

Specs

Clock: 3 tick on, 3 tick off [around 2-3 Hz] Memory read/write delay: 2 ticks

Hardware (planned)

Primary Bus (PBUS)': A bus connected to most components [4bit bus]

Secondary Bus (SBUS): Secondary bus connected to most components [4bit bus]

Instruction Bus (IBUS): Used to transfer instruction data to ALL components. Each component is fitted with a specialised gate that when the right signal is given, turns on the component

Excess Bus (EBUS): A bus for holding an additional 4 bits alongside PBUS or SBUS, used when the output is over 4 bits [4bit bus]

Comparator Bus (CBUS): Holds the results from the last operation by CMP [3bit bus]

Arithmetic Unit (AU): Performs 4-bit addition and subtraction.

Bitwise Unit (BU): Performs 4-bit bitwise operations of OR, AND, XOR, NOT

Comparator (CMP): Performs comparason operations on two inputs and outputs them on CBUS (>, <, ==)

Multiplier (CMP): Performs multiplication operation on two inputs. Output may be over 4 bits, bits 3-7 are loaded onto EBUS

Memory (MEM): Can output to either PBUS or SBUS, contains 16 registers that each store 4 bits (a nibble)

Clock (C): Turns on and off continuesly to keep all components in sync

User input (USIN): 4-bit interface allowing direct user input into the computer

Instruction ROM (IROM): Read only memory, holds upto 32 lines of instructions

Instruction list (4 bit)

Instruction Name: address, arguements , Description


NON: 0, no arguements, "Does nothing"

READ: 1, (arg1: memAddress [4bit], arg2: bus [1bit]), "Reads from memAddress and loads the data into PBUS if arg2 is 0, else loads into SBUS"

WRITE: 2, (arg1: memAddress [4bit], arg2: bus [2bit]), "Writes to memAddress from bus, 00: PBUS, 01: SBUS, 10: EBUS, 11: IBUS"

ADD: 3, (arg1: fromMemAddress [4bit], arg2: fromMemAddress [4bit]), "Performs ADD operation on values stored in MEM, with arg1 and arg2 being their addresses"

SUB: 4, (arg1: fromMemAddress [4bit], arg2: fromMemAddress [4bit]), "Performs SUB operation on values stored in MEM, with ang1 and arg2 being their addresses"

MUL: 5, (arg1: fromMemAddress [4bit], arg2: fromMemAddress[4bit]), "Performs MUL operation on values stored in MEM, with arg1 and arg2 being their addresses. THE OUTPUT OF THIS IS SPLIT INTO TWO BUSES, PBUS or bits 0-3 and EBUS for bits 4-7"

BOR: 6, (arg1: fromMemAddress [4bit], arg2: fromMemAddress[4bit]), "Performs bitwise OR operation on values stored in MEM, with ang1 and arg2 being their addresses"

BAND: 7, (arg1: fromMemAddress [4bit], arg2: fromMemAddress[4bit]), "Performs bitwise AND operation on values stored in MEM, with ang1 and arg2 being their addresses"

BXOR: 8, (arg1: fromMemAddress [4bit], arg2: fromMemAddress[4bit]), "Performs bitwise XOR operation on values stored in MEM, with ang1 and arg2 being their addresses"

BNOT: 9, (arg1: fromMemAddress [4bit]), "Performs bitwise NOT operation on values stored in MEM, with ang1 being the address"

JMP: A, (arg1: line [5bit]), "Unconditionally jumps to the line given"

JMPIF: B, (arg1: line [5bit], arg2: compare [2bit]), "Jumps to line IF CBUS @ arg2 is TRUE"

JMPIFNOT: C, (arg1: line [5bit], arg2: compare[2bit]), "Jumps to line IF CBUS @ arg2 is FALSE"

SWAPBUS: D: no arguements, "Swaps the data in PBUS and SBUS"

HALT: E: no arguements, "Unconditionally halts the program"


Stakeholders

Doytschreal2.png doytschReal

Contributes: design, resources, land (owns Kaniw)

kv4x

Contributes: design

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