Rcomp-kaniw: Difference between revisions

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Rcomp-kaniw is a 4-bit computer project in the town of [[File:kaniw_flag|10px]] [[Aurora:Kaniw|Kaniw]], Ukraine. The machine has been allocated a 2x3 chunk area on the border with the neighbouring town of Cherkassy.
Rcomp-kaniw is a 4-bit computer project in the town of [[File:kaniw_flag.png|10px]] [[Aurora:Kaniw|Kaniw]], Ukraine. The machine has been allocated a 2x3 chunk area on the border with the neighbouring town of Cherkassy.


== Components ==
== Components ==

Revision as of 14:40, 3 December 2023

Rcomp-kaniw is a 4-bit computer project in the town of Kaniw flag.png Kaniw, Ukraine. The machine has been allocated a 2x3 chunk area on the border with the neighbouring town of Cherkassy.

Components

Buses

DataBus 1

Purpose: Loads Data into Arithmetic/Bitwise components.

Size: 4-bit

Writes to: Adder 1, Adder 2, Multiplier, 3-function Bitwise

Reads from: Register 1, Register 2, Register 3, Register 4

DataBus 2

Purpose: Loads Data into Arithmetic/Bitwise components.

Size: 4-bit

Writes to: Adder 1, Adder 2, Multiplier, 3-function Bitwise

Reads from: Register 1, Register 2, Register 3, Register 4

CalcBus 1

Purpose: Loads Data from Arithmetic/Bitwise components to Registers

Writes to: Register 1, Register 2, Register 3, Register 4

Reads from: Adder 1, Adder 2, Multiplier, 3-function Bitwise

==== condition bus

Purpose: Holds a 1 bit value if the previous condition operation was true (==, <, >)

Leads to: Program counter (not written)

Reads from: Comparator

Arithmetic

Adder 1: (CCA design, 4-bit)

Adder 2: (CCA design, 4-bit)

Multiplier: (standard design, 4-bit)

3-function Bitwise: (MUX + AND + OR + XOR gates, 4-bit)

Storage

Register A: (Index: 00, Capacity: 4-bit)

Register B: (Index: 01, Capacity: 4-bit)

Register C: (Index: 10, Capacity: 4-bit)

Register D: (Index : 11, Capacity: 4-bit)

Comparator

Equal to (==): (4-bit)

Greater Than (>): (4-bit)

Less Than (<): (4-bit)

Functions

ALU FUNCTIONS

0: Load DataBus 1 into Adder 1 as input A

1: Load DataBus 2 into Adder 1 as input B

2: Load DataBus 1 into Adder 2 as input A

3: Load DataBus 2 into Adder 2 as input B

4: Load DataBus 1 into Multiplier as input A

5: Load DataBus 2 into Multiplier as input B

6: Load DataBus 1 into Bitwise_Calculator as input A

7: Load Databus 2 into Bitwise_Calculator as input B

8: Run operation: Adder 1 (loads output into CalcBus 1)

9: Run operation: Adder 2 (loads output into CalcBus 1)

A: Run operation: Adder 1 as negative operation (loads output into CalcBus 1)

B: Run operation: Adder 2 as negative operation (loads output into CalcBus 1)

C: Run operation Multiplier (loads output into CalcBus 1)

D: Run operation Bitwise_Calculator as & (and) operation (loads output into CalcBus 1)

E: Run operation Bitwise_Calculator as ^ (xor) operation (loads output into CalcBus 1)

F: Run operation Bitwise_Calculator as | (or) operation (loads output into CalcBus 1)

RAM FUNCTIONS

0: Write USERINPUT on Register 1

1: Write USERINPUT on Register 2

2: Write USERINPUT on Register 3

3: Write USERINPUT on Register 4

4: Read Register 1 into DataBus 1

5: Read Register 1 into DataBus 2

6: Read Register 2 into DataBus 1

7: Read Register 2 into DataBus 2

8: Read Register 3 into DataBus 1

9: Read Register 3 into DataBus 2

A: Read Register 4 into DataBus 1

B: Read Register 4 into DataBus 2

C: Write CalcBus 1 on Register 1

D: Write CalcBus 1 on Register 2

E: Write CalcBus 1 on Register 3

F: Write CalcBus 1 on Register 4

PROGRAM RUNNER FUNCTIONS

REGULAR

0X: Runs the ALU function, where X is the hexidecimal of the ALU function index.

1X: Runs the RAM function, where X is the hexidecimal of the RAM function index.

2-: Does nothing in this clock cycle, practically acts as a wait/sleep.

3XX: Jumps to the instruction at address XX

5XX: Jumps to the instruction if the condition bus is True.

6XX: Jumps to the instruction if the condition bus is False.

COMPARASON

7X: Sets condition bus to True if Register A (index: last 2 bits of X) > Register B (index: first 2 bits of X)

8X: Sets condition bus to True if Register A (index: last 2 bits of X) < Register B (index: first 2 bits of X)

9X: Sets condition bus to True if Register A (index: last 2 bits of X) == Register B (index: first 2 bits of X)

PROGRAM STATUS

A-: Halts the program

B-: Starts the program (this is fired externally, from USERINPUT)

CANVAS

C-: Toggles pixel @ index (index: read from Register 1)

D-: Toggles pixel @ index (index: read from Register 2)

E-: Toggles pixel @ index (index: read from Register 3)

F-: Toggles pixel @ index (index: read from Register 4)

Other Info

When Adder 1 or Adder 2 perform the negation operation, The range of values that a single hexidecimal value can represent shifts from 0 to 15 to -8 to 7, making bit 3 worth -8 and not 8. If bit 3 is still represented as 8, then the negation operation would simply not be true.

Carry-Outs from Adder1 & Adder2 are ignored, as a 5-bit output can't be loaded on a 4-bit bus.

Multipliers can be toggled to either output their first 4 bits, or last 4 bits.

Helpers

Doytschreal2.png DoytschReal: Computer design, Computer construction, Area preperation/Escavation.


Sponsors

Doytschreal2.png DoytschReal: Resources & Components.